1. Field of the Invention
The present invention generally relates to semiconductor fabrication processes. More particularly, the present invention relates to the field of fabricating semiconductor devices having a triple LDD (lateral diffused dopants) structure.
2. Related Art
Semiconductor fabrication processes have made possible the fabrication of advanced integrated circuits on a semiconductor wafer. These semiconductor fabrication processes are complex, requiring extensive control and care to avoid fabricating defective integrated circuits.
Due to the need for high speed and low-voltage, advanced structures have been developed for semiconductor devices such as MOSFETs (metal oxide semiconductor field effect transistor). One such structure is the triple LDD (lateral diffused dopants) structure for the source and drain of the MOSFET. In particular, the triple LDD structure provides a solution to short channel effects.
FIGS. 1A–1F illustrate a conventional method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure. Here, the semiconductor device is a MOSFET 100. As shown in FIG. 1A, a gate structure 10 is formed on the surface of a semiconductor substrate 40. Then, a first implant process is performed to implant a dopant into the semiconductor substrate 40 to form a source 20 and a drain 30. Here, the source 20 and the drain 30 have a single LDD structure.
Moreover, FIG. 1B shows that a first spacer 50 is formed adjacent to the vertical surfaces of the gate structure 10. Furthermore, a second implant process is performed to implant a dopant into the semiconductor substrate 40 to further define the source 20 and the drain 30, as depicted in FIG. 1C. Here, the source 20 and the drain 30 have a double LDD structure.
Additionally, FIG. 1D shows that a second spacer 60 is formed adjacent to the vertical surfaces of the gate structure 10. A third implant process is performed to implant a dopant into the semiconductor substrate 40 to further define the source 20 and the drain 30, as depicted in FIG. 1E. Here, the source 20 and the drain 30 finally have the triple LDD structure.
Furthermore, a silicidation process is performed to form a silicide 70 on the horizontal surface of the gate structure 10 and on the surface of the source 10 and the drain 10 as shown in FIG. 1F, whereas the silicide 70 is used as a contact.
As illustrated in FIGS. 1A–1F, this conventional fabrication method requires three separate implant processes. Each implant process is costly and time consuming. Moreover, the first and second spacers 50 and 60 cover portions of the surface area of the gate structure 10, reducing the surface area of the gate structure 10 that is available for the silicide 70 to be formed. This can lead to higher gate resistance as the width of the gate structure 10 is decreased in advanced semiconductor fabrication applications.